The volume of data transferred between complementary metal oxide semiconductor (CMOS) large scale integrated circuits (LSI) or within a CMOS LSI is increasing, and an optical transmission technology of the order of 10 Tbit/second that employs silicon photonics for achieving a small size, low power consumption, and good compatibility with LSI processes is receiving attention. This transmission technology is demanded to have a transmission rate of 10 Gbit/sec or higher for each channel and parallel transmission in hundreds of channels (see, for example, D. A. B. Miller, “Device Requirements for Optical Interconnects to Silicon Chips”, Proceedings of the IEEE, Vol. 97, pp. 1166-1185, 2009).
An electrical/optical or optical/electrical conversion device has to satisfy both electrical design and optical design, and is likely to degrade in a high frequency area as compared with the response characteristics of a CMOS circuit electrically optimized and fabricated with the same process technology which is applied to the electrical/optical or optical/electrical conversion device. There is a case in which a signal is transferred through capacitive coupling between a photoreceptor and a CMOS circuit to apply a bias exceeding the maximum allowable level of CMOS to the photoreceptor (see, for example, A. S. Narasimha, et al., “An ultra low power CMOS photonics technology platform for H/S optoelectronic transceivers at less than $1 per Gbps”, Conference on Optical Aber Communication (OFC), 2010 and F. Tavernier, and M. S. Steyaert, “A 5.5 Gbit/s optical receiver in 130 nm CMOS with speed-enhanced integrated photodiode”, Proceedings of the ESSCIRC, 2010). However, capacitive coupling blocks signals in a low frequency area.
When the response characteristics of a transfer circuit including optical transmission depends on the frequency area as described above, if a binary digital signal is transmitted as is, a receiving signal is distorted. Such distortion due to suppression in a high frequency area or low frequency area is referred to as intersymbol interference (ISI), which causes a data error.
On the other hand, in an environment to which each channel is exposed, the temperature greatly changes, for example, from −20 degrees to 85 degrees and variations are present in the element characteristic for each channel, so the response characteristics of the transfer circuit is likely to fluctuate from the design value. In addition, it is assumed that the operating frequency of a semiconductor chip may vary depending on the situation in data communication within the semiconductor chip (see, for example, S. Herbert, et al., “Variation-aware dynamic voltage/frequency scaling”, IEEE 15th International Symposium HPCA 2009, pp. 301-312, 2009).
When intersymbol interference is present in the transfer circuit and the characteristic varies as described above, intersymbol interference caused by suppression in a high frequency area is addressed by adaptive equalization (see, for example, Y. Hidaka, et al., “A 4-Channel 1.25-10.3 Gb/s Backplane Transceiver Macro With 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control”, IEEE J. Solid-State Circuits, Vol. 44, pp. 3547-3559, 2009). Adaptive equalization is a dynamic analog processing technology in which distortion for correcting response characteristics is added to a transmitting signal or receiving signal to recover the signal. Intersymbol interference caused by suppression in a low frequency area is addressed by 8b/10b, which is a known technology for devising a transmission protocol (see, for example, A. X. Widmer and P. A. Franaszek, “A DC-Balanced, Partitioned-Block, 8B/10B Transmission Code”, IBM Journal of Research and Development, Vol. 27, pp. 440-451, 1983).
For backplane use or more distant data transmission, the above technology is generally used to reduce data errors. However, adaptive equalization or a protocol such as 8b/10b leads to complicated implementation and is not suited for data communication accompanied by high-density mounting between semiconductor chips or within a semiconductor chip.